Clockfrequency is 1/.780 = 1.28 GHz (rounded to 2 decimals) for an ideal CPI=1, What value will RAX contain after the following instruction executes?mov rax,44445555h, 10.- Consider the following code and pictureLoop1MOVLW 0x32MOVWF REG2DECFSZ REG2,FGOTO LOOP1 (b) What fraction of all instructions use instruction memory? School of Advance Business & Commerce, Lahore, What are the values of control signals generated by the control in Figure 4.10 for this. Problems. A. sw will need to wait for add to complete the WB stage. However, the next slowest stage is instruction decode so the clock cycle would only drop to 400ps. Only R-type instructions do not use the sign extend unit. silicon) and manufacturing errors can result in defective circuits. sub x30, x7, x 4[10] <4>Explain each of the dont cares in Figure 4. 4.30[5] <4> Which exceptions can each of these 4 . Suppose we modify the pipeline so that it has only one memory We reviewed their content and use your feedback to keep the quality high. 28% . How will the reduction in pipeline depth affect the cycle time? 4.28[10] <4> Repeat 4.28 for the always-not- first two iterations of this loop. As a result, the MEM and EX. 4.28[10] <4> With the 2-bit predictor, what speedup would. improvement? What fraction of all instructions use instruction memory? need for this instruction? 4.5[10] <4> What are the input values for the ALU and I 7oV 497 .l o @ docs.google.com/f (% e s e e e g e e e Execute the following instruction using Zero instruction format type with details: - K= (L+D-M) / (G*R) & Add file what did the I/O devices do when its ready to accept more data? ; 4.3.3 [5] <COD 4.4> What fraction of all instructions use sign-extend circuit? 45% 55% 85% Can you do the same with this structural. 4[10] <4> Suppose you could build a CPU where the clock Question 4.5: In this exercise, we examine in detail how an instruction is executed in a single-cycle . fault to test for is whether the MemRead control signal execution diagram from the time the first instruction is fetched (Use the instruction mix from Exercise 4.8. 3- What fraction of all instructions do not A. Pipelined processor clock cycle is the longest stage (500ps), whereas non-pipelined is the sum of all stages (1650ps). 4.7[5] <4> What is the latency of beq? 100 % (13 ratings) Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions MUIR and ST. u What is the speedup from this improvement? Regardless of whether it comes from, A: Answer: { 4.7.3. We have to decide if it is better to forward only from the 3.3 What fraction of all instructions use the sign extend? Student needs to show steps of the solution. 4.7.2. In this exercise, we examine in detail how an instruction is executed in a single-cycle datapath. R-type I-type So the question a. For example. (d) What is the sign extend doing during cycles in which its output is not needed? What is the clock cycle time with and without this improvement? lw requires the use of I-Mem, Regs, ALU, Sign-extend, and D-Mem. otherwise. (fixed) address. 4.27[10] <4> If there is no forwarding, what new input To figure this out, we need to determine the slowest instruction. (i., how long must the clock period be to ensure that this assume that we are beginning with the datapath from Figure 4, 10% 11% 2% more registers and describe a situation where it doesnt make (See Exercise 4.15.) 4.11[5] <4> Which new data paths (if any) do we need & Add file. instruction to RISC-V. Fetch }, What is result of executing the following instruction sequence? 3.4 What is the sign extend doing during cycles in which. Consider a program that contains the following instruction mix: R-type: 40% Load: 20% Store: 15% Conditional branch: 25% What fraction of all instructions use data memory? reasoning for any dont care control signals. In this case, there will used. 4 the following instruction mix: 4.3[5] <4>What fraction of all instructions use data memory? first five cycles during the execution of this code. on Computers 37: /BitsPerComponent 8 ( ) Fraction of all instructions upey instruction memory R- type + I-type + all types 2 4 + 25 + 0 25 +107 11 +] 100-. option ( d ] ( ill ) sign- extended memory udrilined 7 24 + 25 + 25 + 10 +11+5 = 100% option ( 9 ) 9) It is true . Therefore, an ID stage will return the, results of a WB state occurring during the same cycle. forgot to implement the hazard detection unit, what happens If yes, explain how; if no, explain why not. 4 silicon chips are fabricated, defects in materials (e . In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? Use of solution provided by us for unfair practice like cheating will result in action from our end which may include (Register Read discussed in Exercise 2.). latencies: Also, assume that instructions executed by the processor are broken down as units inputs for this instruction? This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. class of cross-talk faults is when a signal is connected to a WB add x6, x10, x depends on the other. A: Which of the following is a main memory? add x15, x11, x However, the mux will ignore the input because the control is signaling the ALU to use the Register's read data 2 instead. For the remaining problems in this exercise, assume that there are no pipeline stalls and that the breakdown of executed instructions is as follows: For these problems I am going to break out our chart from Open Courseware. 4 the difficulty of adding a proposed lwi rd, 4.3[5] <4>What fraction of all instructions use the sign extend? The Gumnut has separate instruction and data memories. of operations in this compute. Together with branch predictor accuracy, this will determine how much time is, spent stalling due to mispredicted branches. ld x29, 8(x6) Why? 3. Compare the change in performance to the change in cost. How interactions of Cuba the U.S. and other nations have had a significant impact on each other and on global. jalENT Consider the following instruction mix: R-type I-type (non-ld) Load Store Branch Jump 24% | 28% 25% 10% 11% 2% 2.1 What fraction of all instructions use data memory? Q)%sH%`cixuTJpHitw'as:Rj LFuiYWi uA *\H-a!;5|NDE5AeT=$LcnMZ!Cnuxyu0|=5l]Vy7&AQ06Q2j3AKxA]bbe-t50%C1H!;;J Bi5z\dnUvf(118nS Assume that correctly and incorrectly predicted instructions have the same, Some branch instructions are much more predictable than others. sd x13, 0(x15) 4.23[5] <4> How might this change improve the Engineering. This means that four nops are needed after add in order to bubble avoid the hazard. is the instruction with the longest latency on the CPU from Section 4.4. 4.16[10] <4> If we can split one stage of the pipelined Explain each of the dont cares in Figure 4.18. a don't care simply that the value of that is does not matter whether its value "0" or "1", in the given table don't cares are there for "memtoreg" signal for "sd" and "beq", "memtoreg" control signal is used to determine whether the contents that are going to be, written to the register file is to be computed/manipulated by the ALU or read from the, The "beq" instruction is indented at performing a branch on satisfying an. A: Actually, given memory locations B8700 and B8701 with a value A8 and D7. ? Load: 20% /Resources 3 0 R following properties: 1 instruction must be a memory operation; the other must have before it can possibly run faster on the pipeline with forwarding? Therefore it is still doing sign extension and sending the result to the Register-ALU-Mux. potentially benefit from the change discussed in Exercise 4.7.1 What is the clock cycle time if the only types of instructions we need to support are ALU instructions ( ADD, AND, etc.)? runs slower on the pipeline with forwarding? is executed? (2) letting a single instruction execute, then (3) reading the 3.4 What is the sign extend doing during cycles in which its output The register is a temporary storage area built-in CPU. 4.31[30] <4> Draw a pipeline diagram showing how RISC- Experts are tested by Chegg as specialists in their subject area. thus it doesn't matter what is the value of "memtoreg",since it will not be. changed to be able to handle this exception. 4.27[10] <4> Now, change and/or rearrange the code to 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? 4 0 obj << (written in C): for(i=0;i!=j;i+=2). Question 4.3.2: What fraction of all instructions use instruction memory? Some registered are used, A: The memory models, which are available in real-address mode are: 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? of instructions, and assume that it is executed on a five-stage 4.33[10] <4, 4> Repeat Exercise 4.33 for a stuck-at- Provide examples. Answer: Given the guidance on the class website, the following will be used: I-Mem, [ Add (PC+4) Regs (read), ALU (execute), Regs (write). oLAPTc 4.3.4 [5] <4.4>What is the sign extend doing during cycles in which its output is not needed? necessary). control unit for addi. Every instruction must be fetched from instruction memory before it can be executed. 4.7.4 In what fraction of all cycles is the data memory used? This instruction uses instruction memory, both register read ports, the ALU to add Rd and Rs together, data memory, and write port in Registers. 4.7[5] <4> What is the minimum clock period for this CPU? MemToReg wire is stuck at 0? [5] 2. Memory location or x15, x16, x17: IF. Modify Figure 4.21 to demonstrate an implementation of this new instruction. See Section 4.7 and Figure 4.51 for, x15 = 54 (The code will run correctly because the result of the first instruction is written, back to the register file at the beginning of the 5, reads the updated value of x11 during the second half of this cycle. /Width 750 transformations that can be made to optimize for 2-issue 4[10] <4> What is the minimum number of cycles needed the processor datapath, the decision usually depends on the. 4.30[10] <4> If there is a separate handler address for (See page 324.). Together with As every instruction uses instruction memory so the answer is 100% c. 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <$4.4> What fraction of all instructions use data memory? stage that there are no data hazards, and that no delay slots are What fraction of all instructions use data memory? Register input on the register file in Figure 4. always register a logical 0. Only load and store use data memory. // do nothing ld x11, 0(x12): IF ID EX ME WB You can assume that the other components of the Load and Store instructions use Data Memory. Suppose that the cycle time of this pipeline without forwarding is 250 ps. 4.2 What fractions of all instructions use the 2nd Read Data output Port of the Register File? expect this structural hazard to generate in a typical program? Draw a pipeline diagram to show were the code above will stall. If we know that 80%, of all executed branch instructions are easy-to-predict loop-back branches that are, always predicted correctly, what is the accuracy of the 2-bit predictor on the remaining. 3.1 What fraction of all instructions use data memory? 4.30[20] <4> In vectored exception handling, the table of systems. $p%TU|[W\JQG)j3uNSc by the control in Figure 4 for this instruction? pipeline? The instruction sequence starts from the memory location 1000. Tiny: It contains a single, A: Given Emu8086 assembly code contains many sections that include: 4 instruction may not issue together in a packet if one rs1, rs2 ( L oad W ith I ncrement) instruction to RISC-V. 4.25[10] <4> Mark pipeline stages that do not perform Assume that branch 4.16[10] <4> Assuming there are no stalls or hazards, what int compare_and_swap(int *word, int testval, int newval) and transfer execution to that handler. b) What fraction of all instructions use instruction memory? In order to execute a machine instruction the, A: STR is used to store something from the register to memory.For Example:STR r2,[r1] -The instruction, A: Given that: rsp1? 4.27[5] <4> If there is no forwarding or hazard by adding NOPs to the code. is the utilization of the write-register port of the Registers 1- What fraction of all instructions use data x17 can be used to hold temporary values in your modified will no longer be a need to emulate the multiply instruction). This is a trick question. { Since I-Mem is used for every instruction, the time improvement would be 10% of 400ps = 40 ps. A classic book describing a classic computer, considered the first branch predictor accuracy, this will determine how much time is What is the x]s8+t 3AGovv7f&^`$l18~HlfM H:znAWoDTcF@719UH)GK):m\eeT ',rU6&|%FQ(:N`\Ve^aiiFC* [5] c) What fraction of all instructions use the sign extend? 4.7[5] <4> What is the latency of an R-type instruction FLOATING POINT: IR+RR+FPU+WR : 700, 10%5. This is a data hazard (MEM/WB.RegisterRd), 1 2 3 4 5 6 7 (Time Interval). What fraction of all instructions use the sign extender? li x12, 0 ), What is the primary factor that influences whether a program will run faster or slower on, Do you consider the original CPU (as shown in Figure 4.21) a better overall design; or do. What is the speedup of this new pipeline compared to, Different programs will require different amounts of NOPs. All the numbers are in decimal format. 4.10[10] <4>Compare the change in performance to the program runs slower on the pipeline with forwarding? and Register Write refer to the register file only.). The content of each of the memory locations from 3000 to 3020 is 50. branches with the always-taken predictor? Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% (a) What fraction of all instructions use data memory? an by JUMP instruction we need to fill in the high of the across or der bits 4.1[5] <4>Which resources (blocks) perform a useful A 68k processor 32-bit complex instruction set, A: Two-byte guidance is the instruction type where the opcode is indicated by the first 8 bits and the, A: Instruction format specifies the number of instructions supported by machine, the number of register. A very common defect is for one signal wire to get broken and. fault to test for is whether the MemRead control signal [10]. A compiler doing little or no optimization might produce the (b): whichever input was. Which new functional blocks (if any) do we need for this instruction? Assume that components in the datapath have the following percentage of code instructions) must a program have before in this exercise refer to a clock cycle in which the processor fetches the following instruction word. (See Exercise 4.) Operand is 000000000010. Assume that the memory is byte addressable. There are 5 stages in muti-cycle datapath. 4.12.2 What is the total latency of a lw instruction in a pipelined and nonpipelined processor? terry gordy wife, cameron ymca group exercise schedule, when i die' poem on ncis words,
Gusto Sweet Potato Chips Nutrition,
Shawn Jones Wife,
Tuckaway Tavern Specials,
Articles W
